View MK1574-01AS_6739997.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

datasheet frame rate communications pll mk1574-01a/b idt? / ics? frame rate communications pll 1 mk1574-01a/b rev c 081309 description the mk1574-01a/b are phase-locked loop (pll) based clock synthesizers, which accept an 8 khz clock input as a reference, and generate many popular communications frequencies. all outputs are frequency locked together and to the input. this allows for the generation of locked clocks to the 8 khz backplane clock, simplifying clock generation and distribution in communications systems. 1) mk1574-01a ? 5 v operation 2) mk1574-01b ? 3.3 v operation idt manufactures the largest variety of clock generators and buffers, and can customize this device for a variety of frequencies. features ? packaged in 16-pin soic ? accepts 8 khz input clock ? output clock rates include t1, e1, t2, e2 ? available in commercial (0o to + 70oc) or industrial (-40 to +85oc) temperature ranges ? for jitter attenuation, use the mk2049 note: eol for non-green parts to occur on 5/13/10 per pdn u-09-01 block diagram input buffer clk1 pll clock synthesis and control circuitry 8 khz input clock fs0-3 4 vdd 2 gnd 2 clk2 clk3 8 khz (recovered) cap1 cap2
mk1574-01a/b frame rate communications pll clock synthesizer idt? / ics? frame rate communications pll 2 mk1574-01a/b rev c 081309 pin assignment output clocks decoding table 0 = connect directly to ground, 1 = connect directly to vdd. 12 1 11 2 10 3 9 iclk 4 vdd 5 vdd 6 nc 7 cap1 8 gnd fs2 fs1 clk3 cap2 clk1 gnd 8kout 16 15 14 13 fs0 fs3 clk2 decode address iclk multiplier clk1 clk2 clk3 fs3:0 (hex) pin1 on-chip pin 10 pin 11 pin 12 0000 0 reserved reserved reserved reserved reserved 0001 1 reserved reserved reserved reserved reserved 0010 2 reserved reserved reserved reserved reserved 0011 3 reserved reserved reserved reserved reserved 0100 4 8.00 khz 2940 23.52 11.76 5.88 0101 5 8.00 khz 1960 15.68 7.84 3.92 0110 6 8.00 khz 2760 22.08 11.04 5.52 0111 7 8.00 khz 2640 21.12 10.56 5.28 1000 8 8.00 khz 1920 15.36 7.68 3.84 1001 9 8.00 khz 6480 51.84 25.92 12.96 1010 a 8.00 khz 2112 16.896 8.448 4.224 1011 b 8.00 khz 1578 12.624 6.312 3.156 1100 c 8.00 khz 8192 65.536 32.768 16.384 1101 d 8.00 khz 6176 49.408 24.704 12.352 1110 e 8.00 khz 1024 8.192 4.096 2.048 1111 f 8.00 khz 772 60176 3.088 1.544
mk1574-01a/b frame rate communications pll clock synthesizer idt? / ics? frame rate communications pll 3 mk1574-01a/b rev c 081309 pin descriptions external components the mk1574-01a/b requires a minimum number of external components for proper operation. an rc network (see the section ?loop bandwidth and loop filter component selection?) should be connected between cap1 and cap2 as close tot he device as possible. decoupling ca pacitors of 0.01f should be connected between vdd and gnd on pins 2, 3, 5 and 7, as close to the device as possible. a series termination resistor of 33 ? may be used close to each clock output pin to reduce reflections. pin number pin name pin type pin description 1 iclk input clock input. connect to an 8 khz clock input. 2 vdd power connect to 3.3 v for 1574-01b, connect to 5 v for 1574-01a. 3 vdd power connect to 3.3 v for 1574-01b, connect to 5 v for 1574-01a. 4 cap1 input connect to a ceramic capacitor and a resistor in series between this pin and cap2. refer to the section ?loop bandwidth and loop filter component selection?. 5 gnd power connect to ground. 6 cap2 power connect to a ceramic capacitor and a resistor in series between this pin and cap1. refer to the section ?loop bandwidth and loop filter component selection?. 7 gnd power connect to ground. 8 fs0 input frequency select 0. determines clk outputs per table above. 9 8kout output recovered 8 khz output clock. can be low jitter, better duty cycle than clock input. 10 clk1 output clock 1 determined by status of fs3:0 per table above. 11 clk2 output clock 2 determined by status of fs3:0 per table above. 12 clk3 output clock 3 determined by status of fs3:0 per table above. 13 fs1 input frequency select 1. determines clk outputs per table above. 14 fs2 input frequency select 2. determines clk outputs per table above. 15 nc ? no connect. do not connect anything to this pin. 16 fs3 input frequency select 3. determines clk outputs per table above.
mk1574-01a/b frame rate communications pll clock synthesizer idt? / ics? frame rate communications pll 4 mk1574-01a/b rev c 081309 absolute maximum ratings stresses above the ratings listed below can cause perm anent damage to the mk1574-01a/b. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd (referenced to gnd) -0.5 v to 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature (commercial) 0 +70 c ambient operating temperature (industrial) -40 +85 c power supply voltage (measured in respect to gnd) +3.13 +5.5 v
mk1574-01a/b frame rate communications pll clock synthesizer idt? / ics? frame rate communications pll 5 mk1574-01a/b rev c 081309 dc electrical characteristics mk1574-01a vdd = 5 v, ambient temperature 0 to +70 c, unless stated otherwise mk1574-01b vdd = 3.3 v, ambient temperature 0 to +70 c, unless stated otherwise parameter symbol conditions min. typ. max. units operating voltage vdd 4.5 5.5 v input high voltage v ih 2v input low voltage v il 0.8 v output high voltage v oh i oh = -4 ma vdd-0.4 v output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i ol = 25 ma 0.4 v operating supply current idd no load 15 ma short circuit current i os each output 100 ma input capacitance c in 7pf parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 3.6 v input high voltage v ih 2v input low voltage v il 0.8 v output high voltage v oh i oh = -4 ma vdd-0.4 v output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i ol = 25 ma 0.4 v operating supply current idd no load 13 ma short circuit current i os each output 100 ma input capacitance c in 7pf
mk1574-01a/b frame rate communications pll clock synthesizer idt? / ics? frame rate communications pll 6 mk1574-01a/b rev c 081309 ac electrical characteristics mk1574-01a vdd = 5 v, ambient temperature 0 to +70 c, unless stated otherwise mk1574-01b vdd = 3.3 v, ambient temperature 0 to +70 c, unless stated otherwise note 1: all multipliers as shown in the table on page two are exact, and are stored in rom on the chip. thermal characteristics parameter symbol conditions min. typ. max. units input frequency f in 8.000 khz output clock rise time t or 0.8 to 2.0 v 1.5 ns output clock fall time t of 2.0 to 0.8 v 1.5 ns output clock duty cycle, high time t dc at vdd/2 40 49 to 51 60 % absolute clock period jitter 1ns actual mean frequency error versus target (note 1) any clock selection 0 0 ppm parameter symbol conditions min. typ. max. units input frequency f in 8.000 khz output clock rise time t or 0.8 to 2.0 v 1.5 ns output clock fall time t of 2.0 to 0.8 v 1.5 ns output clock duty cycle, high time t dc at vdd/2 40 49 to 51 60 % absolute clock period jitter 1ns actual mean frequency error versus target (note 1) any clock selection 0 0 ppm parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 120 c/w ja 1 m/s air flow 115 c/w ja 3 m/s air flow 105 c/w thermal resistance junction to case jc 58 c/w
mk1574-01a/b frame rate communications pll clock synthesizer idt? / ics? frame rate communications pll 7 mk1574-01a/b rev c 081309 loop bandwidth and loop f ilter component selection the series-connected capacitor and resistor between cap1 and cap2 (pins 4 and 6) determine the dynamic characteristics of the phase-locked loop. the capacitor must have very low leakage, therefore a high quality ceramic capacitor is recommended. do not use any type of polarized or electrolytic capacitor. the series connected capacitor and resistor between cap1 and cap2 (pins 4 and 6) determine the dynamic characteristics of the phase-locked loop. the capacitor must have very low leakage, therefore a high quality ceramic capacitor is recommended. do not use any type of polarized or electrolytic capacitor. ceramic capacitors should have c0g or np0 dielectric. avoid high-k dielectrics like z5u and x7 r; these and other ceramics which have piezoelectric properties allow mechanical vibration in the system to incr ease the output jitter because the mechanical energy is converted directly to voltage noise on the vco input. the values of the rc network determine the bandwidth of the pll. the values of the loop filter components are calculated using the constants k1 and k2 from the loop f ilter constants table (page 7). the loop bandwidth is set by the capacitor c and the constant k1 using the formula: the loop damping is set by the resistor r, the ca pacitor c, and the constant k2 using the formula:: for example, to design the loop filter whewn generating 8.192 mhz from 8 khz: 1. from the output clock decoding table (page 2), the address is e. the loop filter constants table (page 7) shows the constants k1 = 0.0516 and k2 = 6.2. 2. a good value for the loop bandwidth is 1/20 the input frequency; where 8 khz/20 = 400 hz. using equation 1, therefore, 3. a good value for the damping factor is 0.707. from equation 2, bw (hz) = c k1 equation 1 r = equation 2; (zeta) is the damping factor c * k2 c k1 400 = c k1 c = 400 0.0516 ( ) 2 = 16.6 nf (16 nf nearest standard value r = = 34.7 k ? (36 k ? nearest standard value) 16e-9 0.707 * 6.2
mk1574-01a/b frame rate communications pll clock synthesizer idt? / ics? frame rate communications pll 8 mk1574-01a/b rev c 081309 loop filter constants this table shows the constants k1 and k2 that are used with the equations on page 6 to calculate the external loop filter components.loop filter contstants for mk1574-01a pc board layout a proper board layout is critical to the successful use of the mk1574-01a/b. in particular, the cap1 and cap2 pins are very sensitive to noise and leakage (cap1 at pin 4 is th e most sensitive). traces must be as short as possible and the capacitor and resistor must be mounted next to the device as shown to the right. the capacitor connected between pins 3 and 5 is the power supply decoupling capa citor. the high frequency output clocks on may benefit from a series 33 ? resistor connected close to the pin (not shown). clock multipliers/accuracies in the table on page 2 are the actual multipliers stored in the mk1574-01a/b rom, which yield the exact values shown for the output clocks. decode address loop filter constants fs3:0 (hex) k1 k2 0000 0 reserved reserved 0001 1 reserved reserved 0010 2 reserved reserved 0011 3 reserved reserved 0100 4 0.0430 7.4 0101 5 0.0527 6.0 0110 6 0.0444 7.2 0111 7 0.0454 7.0 1000 8 0.0533 6.0 1001 9 0.0410 7.8 1010 a 0.0508 6.3 1011 b 0.0587 5.4 1100 c 0.0365 8.7 1101 d 0.0420 7.6 1110 e 0.0516 6.2 1111 f 0.0594 5.4
mk1574-01a/b frame rate communications pll clock synthesizer idt? / ics? frame rate communications pll 9 mk1574-01a/b rev c 081309 package outline and package dimensions (16-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 index area 1 2 16 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 9.80 10.00 .3859 .3937 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
mk1574-01a/b frame rate communications pll clock synthesizer idt? / ics? frame rate communications pll 10 mk1574-01a/b rev c 081309 ordering information *note: eol of non-green parts to occur on 5/13/10 per pdn u-09-01. parts ordered with an ?lf? suffix to the part numb er are the pb-free configur ation and rohs compliant. while the information presented herein has been checked for both accuracy and reliability, idt as sumes no responsibility for ei ther its use or for the infringement of any patents or other rights of third parties, whic h would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those r equiring extended temperature rang e, high reliability, or other extraordinary environmental requirements are not recommended without additio nal processing by idt. idt reserves the right to ch ange any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical me dical instruments. part / order number marking shipping packaging package temperature MK1574-01AS* MK1574-01AS tubes 16-pin soic 0 to +70 c MK1574-01AStr* MK1574-01AS tape and reel 16-pin soic 0 to +70 c MK1574-01ASi* MK1574-01ASi tubes 16-pin soic -40 to +85 c MK1574-01ASitr* MK1574-01ASi tape and reel 16-pin soic -40 to +85 c mk1574-01bs* mk1574-01bs tubes 16-pin soic 0 to +70 c mk1574-01bstr* mk1574-01bs tape and reel 16-pin soic 0 to +70 c mk1574-01bsi* mk1574-01bsi tubes 16-pin soic -40 to +85 c mk1574-01bsitr* mk1574-01bsi tape and reel 16-pin soic -40 to +85 c mk1574-01bsilf 157401bsilf tubes 16-pin soic -40 to +85 c mk1574-01bsilftr 157401bsilf tape and reel 16-pin soic -40 to +85 c
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp> innovate with idt and accelerate your future netw orks. contact: www.idt.com mk1574-01a/b frame rate communications pll clock synthesizer

▲Up To Search▲

Price & Availability of MK1574-01AS

	To Download MK1574-01AS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .